1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a redundancy thereof.
2. Description of Background Information
The cost of a semiconductor integrated circuit depends upon the yield in manufacturing. In order to improve manufacturing yield, redundancy memory cells (or spare memory cells) may be provided apart from a fundamental memory cell (or normal memory cell). If a few defective bits (or defective cells) are found in the fundamental memory cell, a redundancy method may be employed to replace the defective cells with the spare memory cells. However, in a high density integrated memory device having a large capacity of more than 256Mb, a stand-by current defect (DC current leakage) and block failures are frequently generated. Stand-by current defects (DC current leakage) are frequently caused during a manufacturing process due to an increase in chip size, and block failures are frequently generated due to a lack of plate margin for manufacturing (e.g., the width of the line becomes narrower).
A stand-by current defect (DC current leakage) causes a stand-by power dissipation due to current leakage from a defective row. A block failure results when there are a plurality of defective word lines or bits lines, which may be generated, for example, due to a short of a word line or a bit line with another word line or bit line adjacent thereto. Accordingly, since a block failure results from more than one defective word line or bit line, it cannot be repaired unless there is a spare row or spare column which can be substituted for the defective word line or bit line. Accordingly, high density integrated semiconductor memory devices present unique defects and failures which require improved strategies to effectively repair defective memory cells of a die.
A recent technique proposed for solving the redundancy problems associated with large capacity, high density semiconductor memory devices is disclosed by M. Asakura et al. and Mitsubishi Electric Corporation in a paper entitled "A 34ns 256Mb DRAM with Boosted Sense-Ground Scheme", ISSCC, pp. 140-141 (1994), the content of which is hereby incorporated herein by reference in its entirety. FIG. 1 illustrates the redundancy method disclosed in this paper. FIG. 1 includes a sub memory cell array 30 which comprises a normal sub memory cell array 320 and a spare sub memory cell array 340. Normal sub memory cell array 320 comprises a plurality of sub blocks, ranging from SUB BLOCK 1 to SUB BLOCK 32; and spare sub memory cell array 340 comprises a plurality of spare sub blocks, ranging from SPARE SUB BLOCK 1 through SPARE SUB BLOCK 32.
A normal row decoder NRD and a spare row decoder SRD are respectively connected to normal sub memory cell array 320 and spare sub memory cell array 340 for decoding rows within the respective arrays. A column decoder CD is shown in FIG. 1 to the right of sub memory cell array 30, and is provided for decoding the columns within either of normal sub memory cell array 320 and spare sub memory cell array 340.
A fuse box 10 is provided and has an output connected to each of a plurality of decoding elements provided within spare row decoder SRD for respective spare sub blocks. Normal row decoder NRD and spare row decoder SRD comprise a common input which receives a voltage signal VWLH, for providing a boosting voltage to a word line of the memory cell. That voltage is coupled to each of the plural row decoding elements through either a fuse 1 or a transistor switch 2.
If a stand-by current defect (i.e., a DC current leakage) is generated in the last sub block (SUB BLOCK 32) included in normal sub memory cell array 320, its corresponding row decoder fuse 1 is blown out, so that the voltage signal VWLH is not provided to the word line corresponding to that sub block. Consequently, the path of the leakage current is severed. In addition, the leakage path of the stand-by current may be formed by a bridge defect between a cell plate and a bit line. When such a bridge defect exists, while a connection is established between plate voltage VCP to each sub block of normal sub memory cell array 320 through a column decoder fuse 3 (or to a spare sub block through the use of a column decoder transistor switch 4), the path of the stand-by leakage current may be severed by turning on a column detector transistor switch 4 connected to the corresponding spare sub block, instead of blowing a column detector fuse 3 of the corresponding normal sub block.
FIG. 1A illustrates a detailed block diagram of the prior art layout. Row decoders "r1" are assigned so as to correspond to each sub block (for example, a set of sixteen 256 Kb unit array has a memory capacity of 4Mb) "sub1," one by one. Column decoders "c1" are assigned so as to correspond to each unit array, each having capacity of 256Kh, one by one. The above unit array is arranged along same column within a plurality of the sub blocks. Thus, the spare memory cell array, SMCA, independently uses the row decoder "sr1" for redundancy, autonomous from the above row decoder "r1" which is assigned to the normal memory cell array NMCA, and uses the column decoder "c1" in common with the normal memory cell array NMCA. In a memory device having a memory capacity of 256Mb, the sub block connected to a row decoder has a memory capacity of 2Mb; whereas, in a memory device having a memory capacity of 1Gb, the sub block connected to a row decoder has a memory capacity of 4Mb as shown in FIG. 1A. For example, therefore, in case that defective cells are detected in five sub blocks "sub 1", in order to carry out a repair operation block by block, space sub memory cell arrays of 10Mb and 20Mb are respectively required in the semiconductor memory devices of 256Mb and 1Gb. Since the spare sub memory cell arrays of 20Mb is required in the memory system as shown in FIG. 1A, five spare sub blocks "rsub 1" are employed to carry out the repair operation. As a result, in the high density integrated semiconductor memory device having a large capacity, the redundancy efficiency becomes significantly low so as to inevitably cause an increase in the chip size.
The illustrated conventional redundancy method, as described above, presents several disadvantages. In order to replace a normal sub block unit in memory cell array 30, a spare sub block must be available which is connected to the same common row decoder. In a semiconductor memory device having a large capacity of more than 256Mb, the sub memory cell array 320 connected to one row decoder will generally have a memory capacity of about 2Mb. In a semiconductor memory device of 1Gb, the sub memory cell array has a memory capacity of 4Mb. Therefore, for example, if five sub memory cell arrays have a stand-by current defect (i.e., a current leakage), in order to repair such a defect, spare sub memory cell arrays of 10Mb and 20Mb are respectively required in each of the above semiconductor devices (of 256Mb and 1Gb). Therefore, the size of the chip will be significantly increased. Another disadvantage occurs when a leakage current is generated in one normal sub block, since the entire sub memory cell array 30 must be replaced by a spare sub memory cell array. Accordingly, redundancy efficiency is significantly low.
A further disadvantage is that the spare sub block shares a column decoder CD with its corresponding normal sub block, and redundancy information based upon the fuse program is not applied to column detector CD. Accordingly, if a defect is generated in two or more normal sub blocks within a common column, it is impossible to replace the defective memory cell array 30 with spare sub blocks which are arranged only according to their row.
In addition, in the conventional redundancy method illustrated in FIG. 1, there is no ability to properly repair leakage current defects generated in parts of the memory circuitry not corresponding to a particular memory cell. Such defects may occur, for example, in: a core circuit area (e.g., an area where there is a sense amp), a row decoder, a column decoder, bit lines, and data input/output lines.
In addition, end differences in peripheral areas of the circuit are lower than such differences where the memory cells are arranged. Accordingly, dirt particles are easily deposited during the manufacturing process, increasing the occurrence of bridge defects.